Eng-Deg Design Method

Detalles de la oferta

Our vision is to transform how the world uses information to enrich life for all.
Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever.
Job Summary: We are seeking a highly motivated Design Engineer to join our team at Micron Technology.
As a Design Engineer, you will be responsible for designing and analyzing digital and analog circuits used in the development of memory products.
Main Responsibilities: Design and analyze digital and analog circuits used in memory product development.
Develop groundbreaking silicon-to-systems solutions, including technology development, advanced memory designs, and product development.
Collaborate with cross-functional teams to drive innovation and improve design quality.
Evaluate and identify best-known practices and communicate to all DRAM teams.
Perform verification processes using industry-standard simulators and analyze results to confirm simulation to silicon correlation.
Drive innovation into future memory generations within a dynamic work environment.
Requirements: BS with 2+ years' experience or MS Proven knowledge/experience of CMOS Circuit Design and Device Physics Design digital and analog circuits using CMOS logic gates and transistors.
Create floorplans that optimize for the best circuit placement, signal routing, and power delivery.
Using Spice and Verilog, simulate to verify proper circuit operation and analyze circuits for power consumption, speed performance, and reliability.
Model layout parasitics in the simulation and verify proper signal routing and power supply connections.
Proven knowledge/experience with Verilog modeling and simulation tools.
Proven knowledge/experience of state machine logic/design verification techniques.
Preferred Qualifications: Good understanding of ASIC design flow including RTL design, verification, logic synthesis and timing analysis.
Experience in ASIC timing constraints generation and timing closure using STA tools (Primetime) and the associated design flow.
Experience in RTL development for logic or mixed-signal circuits.
What We Offer: A collaborative environment and opportunities for growth and development.
A competitive salary: $120,000 - $180,000 per year.
A comprehensive benefits package, including medical, dental, and vision insurance, 401(k) matching, and paid time off.
The opportunity to work with cutting-edge technology and innovative products.


Salario Nominal: A convenir

Fuente: Talent_Ppc

Requisitos

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