.37447BRMEXICO-Guadalajara**Job Description and Requirements**At Synopsys, we are at the heart of the innovations that change the way we work and play. Self-driving cars. Artificial Intelligence. The cloud. 5G. The Internet of Things. These breakthroughs are ushering in the Era of Smart Everything. In addition to the traditional EDA tools and IP we also provide design services to enable our customers with end-to-end SoC design solution in advanced technology nodes. If you share our passion for innovation, we want to meet you.**Responsabilities**:- Developing specifications, micro-architecture, and RTL design of mission critical blocks in collaboration with the chip architect- Collaborating with the verification team on test plans, debug support and coverage closure to ensure high quality RTL and first pass silicon success- Providing timing constraints and STA support to the Physical Design team through timing closure- Providing post silicon lab bring-up and debug support- Provide guidance to less experience team members**Requirements**:Typically requires a minimum of 5 years of related experience. Possesses a solid understanding of specialization area plus working knowledge of one other related area. Resolves issues in creative ways. Exercises autonomous judgment in selecting methods and techniques to obtain solutions. Executes projects from start to completion. Contributes to moderately complex aspects of a project. Establishes and develops recommendations to solutions. Works on team-energized or task-oriented projects. May guide more junior peers with aspects of their job. Networks with senior internal and external personnel in own area of expertise.**Qualifications**:- 4-7 years of experience in the related area- Logic design experience writing RTL in Verilog/SystemVerilog- Previous development of a FPGA and ASIC designs- Capture and documentation of design requirements- Design partitioning and micro-architecture for IP re-use- Knowledge on designing state machines, FIFOs, high speed data paths and arbitration logic and DFT- Knowledge of high speed protocols: PCIE Gen 3 5, SRIO, InfiniBand, etc.- Experience with configurable RTL for IP re-use.- Setup and execution of synthesis and timing closure flows- Fundamental verification skills and interaction with a verification team- Solid understanding of standard design methods- Synchronous design practices- Clocking domain crossing techniques.- Experience with automation through scripting such as Perl, Python, Tcl & Make- Solid working experience with industry standard CAD tools (i.E Design Compiler)About SynopsysAt Synopsys, we're at the heart of the innovations that change the way we work and play. Self-driving cars. Artificial Intelligence. The cloud. 5G. The Internet of Things. These breakthroughs are ushering in the Era of Smart Everything. And we're powering it all with the world's most advanced technologies for chip design and software security