The world is transforming and so is Intel. Here at Intel, we believe the world needs technology that can enrich the lives of every person on Earth.
The Advanced Architecture Development Group (AADG - GDC) is a CPU Core development team in Guadalajara, Mexico. We believe that developing these technologies takes a team of exceptionally talented individuals who work together to visualize, innovate, and make the future of computing possible. If you are excited about advanced development of breakthrough technologies for future-generation CPU cores, we welcome you to join us; to do something wonderful.
The focus of this role is to be part of a team of CPU Logic Design Engineers to implement new and existing features for Intel's next generation CPU IP resulting in bug free, synthesizable and timing compliant IP design. You will be responsible for developing the logic design, register transfer level (RTL) coding and formal verification; as well as definition of architecture and microarchitecture for features of the CPU being designed.
Role responsibilities include although not limited to:
- Performs logic design Register Transfer Level (RTL) coding and simulation to generate cell libraries, functional units, and subsystems for inclusion in full chip designs.
- Performs first level verification of it's own design units.
- Applies various strategies, tools, and methods to write RTL and optimize logic to qualify the design to meet power, performance, area, and timing goals as well as design integrity for physical implementation.
- Supports SoC customers to ensure high-quality integration of the CPU block.
- Documents micro architectural specs (MAS) of the CPU features being designed.
- Reviews the verification plan and implementation to ensure design features are verified correctly and resolves and implements corrective measures for failing RTL tests to ensure correctness of features.
- Influences test plan and test strategy for the SoC components in tight collaboration with the Verification counterpart.
**Qualifications**:
Minimum qualifications:
- Bachelor's degree or a Master's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field.
- 2+ years of experience, coursework and/or Internships in the following areas:
- Strong background in digital design, ASIC design flow and computer architecture.
- Past industry experience or in depth academia research for Marsters/PhD in IP logic design.
- Experience with programming/scripting languages like C/C++, Perl, Ruby, Python, and Unix (Linux).
- Experience with hardware description languages (such as VHDL, Verilog, System Verilog).
- Skills pertaining to Pre-Silicon Logic Design, including expertise in: System Verilog for Design, Logical Synthesis, STA, Timing closure, Linting, Design for Low Power techniques and Verification skills such as: test development, execution, debug.
Preferred Qualifications:
- Projects or internships in CPU or ASIC verification and functional modeling
- Experience with scripting languages like Python Perl
- Familiarity with x86 or advanced CPU Datapath components Design
- Relevant courses: Computer Architecture, Digital Design, Verification Logic Design, Programming Languages and Data Structures.
**Inside this Business Group**:
The Advanced Architecture Development Group (AADG) is a CPU Core development team in Portland, Oregon. If you are excited about advanced development of breakthrough technologies for future-generation CPU cores, please join us. We believe that developing these technologies takes a team of exceptionally talented individuals who work together to visualize, innovate, and make the future of computing possible. Join us to do something wonderful!
**Posting Statement**:
All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.
**Benefits**:
We offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock, bonuses, as well as, benefit programs which include health, retirement, and vacation. Find more information about all of our Amazing Benefits here.
**Working Model**:
This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. **In certain circumstances the work model may change to accommodate business needs.**
JobType
Hybrid
