Design Senior Analog Layout Engineer

Detalles de la oferta

We are hiring for Product Engineering roles including but not limited to, Component Validation, Module Validation, Media Health, Yield & Quality, SCG, System Software/Automation**Design Senior analog layout engineer****Role and Responsibilities**- Responsible for Design and development of IP layouts used in DRAM chips.- Perform layout verification like LVS/DRC/EM, quality check and documentation.- Responsible for on-time delivery of block-level layouts with acceptable quality.- Demonstrate leadership Skill in planning, area/time estimation, scheduling, delegation and execution to meet project schedule/milestones in multiple project environment.- Guide and lead junior team-members in their execution of Sub block-level layouts & review their work.- Contribute to effective project-management.- Plan and document your layout, presenting material for global teams to review- Optimally connect with engineering teams in India, Japan the US, and other global teams to ensure the success of the layout project.**Qualification/Requirements**- Must have 8 + years of experience in layout designs in advanced CMOS process.- Should be able to perform IP layout development and physical verification activities for complex designs as per provided specifications.- Should have expertise in layout area and routing optimization, design rules, yield and reliability issues.- Good understanding of layout fundamentals i.E. Electro-migration, Latch-up, coupling, crosstalk, IR-drop, parasitic analysis, matching, shielding, etc.- Should have adequate knowledge of schematics, interface with circuit designer and CAD team.- Understanding layout effects on the circuit such as speed, capacitance, power and area etc.,- Excellent in problem-solving skills in solving area, power, performance and physical verification of custom layout.- Experience with Cadence tools including Virtuoso schematic editor Virtuoso layout L, XL & Verification tools like Mentor Calibre- Proficient in Device Matching, Parasitic Analysis, Electron Migration, and Isolation Techniques.- Should have leadership qualities and able to do multi-tasking as required.- Should be able to work in a team environment and able to guide and provide technical support to the fellow team members.- Self-motivated, hardworking, goal-oriented and excellent verbal and written communication skills.- Knowledge of Skill coding and layout automation is a plus.**Education**BE/BTech or MTech in Electronic/VLSI Engineering or equivalent; we will also consider exceptionally talented Diploma holders in electronic or VLSI engineeringTipo de puesto: Tiempo completoSueldo: $60,000.00 - $70,000.00 al mesTipo de jornada:- Turno de 8 horasLugar de trabajo: Empleo presencial


Fuente: Jobtome_Ppc

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