you will be responsible for designing and analyzing digital and analog circuits used in the development of memory products. We are engaged in developing groundbreaking silicon-to-systems solutions – right from technology development and advanced memory designs to product development, systems design, and validation resulting in world-class memory solutionsWhat's Encouraged Daily:
- Contributing to the development of new product, design flows and methodologies by assisting with the overall design, layout, and optimization of Memory/Logic/Analog circuits.
- Evaluate and identify the best-known practices and communicate to all DRAM teams.
- Performing verification processes with modeling and simulation using industry-standard simulators. Analyze results to confirm simulation to silicon correlation.
- Overseeing the layout process including floor planning, placement, and routing.
- Contributing to cross-group communication to work towards standardization and group success.
- Proactively solicit guidance from Standards, CAD, modeling, and verification groups to improve the design quality.
- Driving innovation into the future Memory generations within a dynamic work environmentHow To Qualify:
- BS with 3+ years' experience or MS with 2+ years' experience.
- Knowledge/experience of CMOS Circuit Design and Device Physics
- Design digital or analog circuits using CMOS logic gates and transistors.
- Create floorplans that optimize for the best circuit placement, signal routing, and power delivery.
- Using Spice and Verilog, simulate to verify proper circuit operation. Analyze circuits for power consumption, speed performance, and reliability.
- Model layout parasitics in the simulation and verify proper signal routing and power supply connections.
- Proven knowledge/experience with Verilog modeling and simulation tools
- Proven knowledge/experience of state machine logic/design verification techniquesPreferred Qualifications:
- Good understanding of ASIC design flow including RTL design, verification, logic synthesis and timing analysis.
- Experience in ASIC timing constraints generation and timing closure using STA tools (Primetime) and the associated design flow.
- Experience in RTL development for logic or mixed-signal circuits. Sueldo: $50,000 MXN Mensual Categoría: Tecnologías de la Información - Sistemas Subcategoría: Pruebas - Control de calidad Localidad: México-Jalisco-Guadalajara Sector: Servicios Giro: Servicios de Outsourcing, Head Hunter y Consultoría en R.H. (Servicios) Tipo de contratación: Tiempo completo - Permanente Número de oferta: 19312990 #J-18808-Ljbffr