As a DRAM Engineering Group Technology (DEGT) Layout Designer at Micron Technology, Inc., you will play a pivotal role in transforming the world's most advanced memory and semiconductor technologies.We are seeking an experienced DRAM Design Tech Layout Engineer to join our team of visionaries and scientists. With a relentless focus on customer satisfaction, technology leadership, and operational excellence, we deliver high-performance DRAM, NAND, and NOR memory and storage products through our Micron and Crucial brands.Your primary responsibilities will include translating schematics into layout used for the creation of fabrication reticules. You will be required to meet all engineering and process-related criteria needed for assigned Dram products. To ensure success, you will organize and prioritize logistics and resource allocations to meet scheduled deadlines and proactively develop methodologies for issue resolution.You will work closely with Design and other engineering groups to apply multiple layout techniques for the design and verification of digital and analog circuits. This will involve understanding various circuit design protocols, different fab processes, mask generation techniques, and tapeout processes and procedures.Key Responsibilities:Responsible for Design and development of IP layouts used in DRAM chips.Perform layout verification like LVS/DRC/EM, quality check, and documentation.Ensure on-time delivery of block-level layouts with acceptable quality.Demonstrate leadership skills in planning, area/time estimation, scheduling, delegation, and execution to meet project schedule/milestones in multiple project environments.Guide and lead junior team members in their execution of sub-block-level layouts and review their work.Contribute to effective project management.Plan and document your layout, presenting material for global teams to review.Optimally connect with engineering teams in India, Japan, the US, and other global teams to ensure the success of the layout project.Requirements:Must have 3+ years of experience in layout designs in advanced CMOS process.Should be able to perform IP layout development and physical verification activities for complex designs as per provided specifications.Should have expertise in layout area and routing optimization, design rules, yield, and reliability issues.Good understanding of layout fundamentals, including electro-migration, latch-up, coupling, crosstalk, IR-drop, parasitic analysis, matching, shielding, etc.Should have adequate knowledge of schematics, interface with circuit designers, and CAD teams.Understanding layout effects on the circuit such as speed, capacitance, power, and area, etc.Excellent problem-solving skills in solving area, power, performance, and physical verification of custom layout.Experience with Cadence tools, including Virtuoso schematic editor, Virtuoso layout, L, XL & Verification tools like Mentor Calibre - Proficient in Device Matching, Parasitic Analysis, Electron Migration, and Isolation Techniques.Should have leadership qualities and be able to do multi-tasking as required.Should be able to work in a team environment and provide technical support to fellow team members.Self-motivated, hardworking, goal-oriented, and excellent verbal and written communication skills.Knowledge of coding and layout automation is a plus.Education:BE/BTech or MTech in Electronic/VLSI Engineering or equivalent; we will also consider exceptionally talented Diploma holders in electronic or VLSI engineering.Salary Range: $120,000 - $180,000 per annum, depending on experience