.Our vision is to transform how the world uses information to enrich life for all.Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever.For more than 43 years, Micron Technology, Inc. has redefined innovation with the world's most advanced memory and semiconductor technologies. We're an international team of visionaries and scientists, developing groundbreaking technologies that are transforming how the world uses information to enrich life.As an Analog Verification Lead Engineer at Micron Technology, Inc., you will be responsible for leading a team to develop groundbreaking analog verification solutions and drive the adoption of new analog verification methodologies across the various DRAM verification project teams.We are looking for an IP Layout Engineer in our DRAM and Emerging Memory Group (DEG) at Micron Technology, Inc. As an IP Layout Engineer, you will be working with an exceptionally talented, passionate core team collaborating with peer teams across Micron's global footprint in a multiple projects-based environment.Role and ResponsibilitiesResponsible for design and development of IP layouts used in DRAM chips.Perform layout verification like LVS/DRC/EM, quality check, and documentation.Responsible for on-time delivery of block-level layouts with acceptable quality.Demonstrate leadership skills in planning, area/time estimation, scheduling, delegation, and execution to meet project schedule/milestones in a multiple project environment.Guide and lead junior team members in their execution of sub block-level layouts & review their work.Contribute to effective project management.Plan and document your layout, presenting material for global teams to review.Connect with engineering teams in India, Japan, the US, and other global teams to ensure the success of the layout project.Qualification/RequirementsMust have 5+ years of experience in layout designs in advanced CMOS process.Should be able to perform IP layout development and physical verification activities for complex designs as per provided specifications.Should have expertise in layout area and routing optimization, design rules, yield, and reliability issues.Good understanding of layout fundamentals i.E. Electro-migration, Latch-up, coupling, crosstalk, IR-drop, parasitic analysis, matching, shielding, etc.Should have adequate knowledge of schematics, interface with circuit designer and CAD team.Understanding layout effects on the circuit such as speed, capacitance, power, and area.Excellent problem-solving skills in solving area, power, performance, and physical verification of custom layout
