Dram Design Senior Layout Engineer

"Transforming information into intelligence is our goal.We innovate memory and storage solutions at Micron Technology, leading the world in accelerating information into intelligence.Our team sees innovation in the way we work, with diverse teams and a collaborative environment.We're looking for a talented IP Layout Engineer in our DRAM and Emerging memory Group (DEG) to join our team.Key Responsibilities:Design and develop IP layouts for DRAM chips.Verify layouts using LVS/DRC/EM, quality check, and documentation.Deliver block-level layouts on time with acceptable quality.Lead junior team members in their execution of sub-block layouts and review their work.Contribute to project management and planning.Requirements:5+ years of experience in layout design in advanced CMOS processes.Expertise in layout area and routing optimization, design rules, yield, and reliability issues.Knowledge of layout fundamentals, schematics, and interface with circuit designers and CAD teams.Proficiency in Cadence tools, including Virtuoso schematic editor and Virtuoso layout tools.Leadership qualities, problem-solving skills, and excellent communication skills.Education: BE/BTech or MTech in Electronic/VLSI Engineering or equivalent; or exceptionally talented Diploma holders in electronic or VLSI engineering."