IP Layout Engineer Job DescriptionMicron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever.We are looking for an IP Layout Engineer in our DRAM and Emerging memory Group (DEG) at Micron Technology, Inc. As an IP Layout Engineer, you will be working with an exceptionally talented, passionate core team collaborating with peer teams across Micron's global footprint, in a multiple projects-based environment.Key Responsibilities:Design and development of IP layouts used in DRAM chips.Perform layout verification like LVS/DRC/EM, quality check and documentation.Responsible for on-time delivery of block-level layouts with acceptable quality.Demonstrate leadership skills in planning, area/time estimation, scheduling, delegation and execution to meet project schedule/milestones in multiple project environments.Guide and lead junior team members in their execution of sub-block level layouts & review their work.Contribute to effective project management.Plan and document your layout, presenting material for global teams to review.Optimally connect with engineering teams in India, Japan, the US, and other global teams to ensure the success of the layout project.Qualification Requirements:Must have 5+ years of experience in layout designs in advanced CMOS process.Should be able to perform IP layout development and physical verification activities for complex designs as per provided specifications.Should have expertise in layout area and routing optimization, design rules, yield and reliability issues.Good understanding of layout fundamentals i.e. Electro-migration, Latch-up, coupling, crosstalk, IR-drop, parasitic analysis, matching, shielding, etc.Should have adequate knowledge of schematics, interface with circuit designer and CAD team.Understanding layout effects on the circuit such as speed, capacitance, power and area etc.Excellent problem-solving skills in solving area, power, performance and physical verification of custom layout.Experience with Cadence tools including Virtuoso schematic editor Virtuoso layout L, XL & Verification tools like Mentor Calibre - Proficient in Device Matching, Parasitic Analysis, Electron Migration, and Isolation Techniques.Should have leadership qualities and able to do multi-tasking as required.Should be able to work in a team environment and able to guide and provide technical support to fellow team members.Self-motivated, hardworking, goal-oriented and excellent verbal and written communication skills.Knowledge of skill coding and layout automation would be plus.Education:BE/BTech or MTech in Electronic/VLSI Engineering or equivalent; we will also consider exceptionally talented Diploma holders in electronic or VLSI engineering.