Our vision is to transform how the world uses information to enrich life for all.Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever.DRAM Design Analog layout engineerWe are an international team of visionaries and scientists, developing groundbreaking technologies that are transforming how the world uses information to enrich life. For more than 43 years, Micron Technology, Inc. has redefined innovation with the world's most advanced memory and semiconductor technologies.As a DRAM Engineering Group Technology (DEGT) Layout Designer at Micron Technology, Inc., you will be responsible for translating schematics into layout used for the creation of fabrication reticles. You will meet all engineering and process related criteria needed for an assigned Dram product, organizing and prioritizing logistics and resource allocations to meet scheduled deadlines.You will proactively develop methodologies for issue resolution, working with Design and other engineering groups to apply multiple layout techniques for the design and verification of digital and analog circuits. You will understand various circuit design protocols, different fab processes, mask generation techniques, and tapeout processes and procedures.While experience may not exhibit all of the characteristics/skills listed below today, we are highly interested in a teammate motivated to grow in technical breadth and depth. If you are open to learning while being a valued member of a team of premier engineers, we are determined to help build upon your existing foundation, while rapidly growing your individual and collaborative skills in this exciting opportunity.Role and ResponsibilitiesDesign and development of IP layouts used in DRAM chips.Layout verification like LVS/DRC/EM, quality check and documentation.On-time delivery of block-level layouts with acceptable quality.Leadership skill in planning, area/time estimation, scheduling, delegation and execution to meet project schedule/milestones in multiple project environment.Guiding and leading junior team-members in their execution of Sub block-level layouts & review their work.Contribute to effective project-management.Plan and document your layout, presenting material for global teams to review.Optimally connect with engineering teams in India, Japan the US, and other global teams to ensure the success of the layout project.Qualification/Requirements3+ years of experience in layout designs in advanced CMOS process.Ability to perform IP layout development and physical verification activities for complex designs as per provided specifications.Expertise in layout area and routing optimization, design rules, yield and reliability issues.Good understanding of layout fundamentals i.e. Electro-migration, Latch-up, coupling, crosstalk, IR-drop, parasitic analysis, matching, shielding, etc.Adequate knowledge of schematics, interface with circuit designer and CAD team.Understanding layout effects on the circuit such as speed, capacitance, power and area etc.Excellent problem-solving skills in solving area, power, performance and physical verification of custom layout.Experience with Cadence tools including Virtuoso schematic editor Virtuoso layout L, XL & Verification tools like Mentor Calibre- Proficient in Device Matching, Parasitic Analysis, Electron Migration, and Isolation Techniques.Leadership qualities and ability to do multi-tasking as required.Team player with excellent verbal and written communication skills.Knowledge of Skill coding and layout automation is a plus.EducationBE/BTech or MTech in Electronic/VLSI Engineering or equivalent; we will also consider exceptionally talented Diploma holders in electronic or VLSI engineering.