Ip Logic Design Associate

Detalles de la oferta

The IP (Intellectual Property) Logic Design Associate develops Pre-Silicon functional validation tests to verify that the system will meet design requirements.They also create test plans for RTL validation, defining and running system simulation models, and finding and implementing corrective measures for failing RTL tests. They will analyze and use results to modify testing.**Qualifications**Requirements listed below would be obtained through a combination of schoolwork/classes/research and/or relevant previous job and/or internship experiences.**Minimum Qualifications**:- 6+ months of experience running tests on microcontrollers.**Preferred Qualifications**:- 1+ year of experience in HDL (Hardware Description Language) like System Verilog and other related languages.- Experience debugging RTL.- Understanding of power strategies, Clock/Reset domain crossing, and synthesis process.- Knowledge on Pre-Si verification.- Knowledge in FPGAs.**Inside this Business Group**The Programmable Solutions Group (PSG) was formed from the acquisition of Altera. As part of Intel, PSG will create market-leading programmable logic devices that deliver a wider range of capabilities than customers experience today. Combining Altera's industry-leading FPGA technology and customer support with Intel's world-class semiconductor manufacturing capabilities will enable customers to create the next generation of electronic systems with unmatched performance and power efficiency. PSG takes pride in creating an energetic and dynamic work environment that is driven by ingenuity and innovation. We believe the growth and success of our group is directly linked to the growth and satisfaction of our employees. That is why PSG is committed to a work environment that is flexible and collaborative, and allows our employees to reach their full potential.**Work Model for this Role**This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site.


Salario Nominal: A convenir

Fuente: Jobtome_Ppc

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