Job Title: DRAM Engineering Group Methodology (DEGDT) Layout DesignerAbout Us: Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever.Our Opportunity Summary: For more than 43 years, Micron Technology, Inc. has redefined innovation with the world's most advanced memory and semiconductor technologies.
We're an international team of visionaries and scientists, developing groundbreaking technologies that are transforming how the world uses information to enrich life.Description: As a DRAM Engineering Group Methodology (DEGDT) Layout Designer at Micron Technology, Inc., you will be responsible for translating schematics into layout used for the creation of fabrication reticules.
You will meet all engineering and process-related criteria needed for an assigned Dram product.
You will organize and prioritize logistics and resource allocations to meet scheduled deadlines, and proactively develop methodologies for issue resolution.
In this role, you will work with Design and other engineering groups to apply multiple layout techniques for the design and verification of digital and analog circuits.
You will understand various circuit design protocols, different fab processes, mask generation techniques, and tapeout processes and procedures.Role and Responsibilities:Design and Verify All Levels of Analog and Digital Layout.Use computer-aided design software (i.e., Cadence, Calibre, etc.
).Work with Design Engineers to floor plan and design layout.Understand and follow verification protocols.Apply custom and/or automated layout techniques to design pitch, array, and peripheral layout for digital and analog circuits.Develop and Maintain Technical Knowledge.Interface with design engineering to understand layout methodology.Possess basic understanding of circuit design.Understand tape out processes and procedures.Apply fab process knowledge, including Design for Manufacturing (DFM) and Optical Proximity Correction (OPC).Manage and Participate in Project-Based Environment.Prioritize tasks to attain schedules and deadlines.Proactively develop methodologies to resolve issues.Qualification/Requirements:2+ years of experience in layout designs in CMOS process.Good understanding of layout fundamentals i.e.
Electro-migration, Latch-up, coupling, crosstalk, IR-drop, parasitic analysis, matching, shielding, etc.Knowledge of schematics, interface with circuit designer and CAD team.Problem-solving skills in solving area, power, performance and physical verification of custom layout.Knowledge of Cadence tools including Virtuoso schematic editor Virtuoso layout L, XL & Other Verification tools like Mentor CalibreShould be able to work in a team environment and able to guide and provide technical support to the fellow team members.Education: BE/BTech or MTech in Electronic/VLSI Engineering or equivalent; we will also consider exceptionally talented Diploma holders in electronic or VLSI engineering.Estimated Salary: $120,000 - $180,000 per year depending on qualifications and experience.