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**Our vision is to transform how the world uses information to enrich life for**_all_**.
**Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever.
**Our Opportunity Summary**:For more than 43 years, Micron Technology, Inc. has redefined innovation with the world's most advanced memory and semiconductor technologies.
We're an international team of visionaries and scientists, developing groundbreaking technologies that are transforming how the world uses information to enrich life.Our team vision is a continuing desire to develop your skills working in an inclusive diverse environment of multicultural Teams across worldwide geographies!
Enabling the creative career path you deserve with a collaborative environment and groundbreaking technology and growing upon your imagination and creativity.
**(Disclaimer)**: While you may not exhibit all of the characteristics/skills listed below today, we are highly interested in a teammate motivated to grow in technical breadth and depth.
Suppose you are open to learning while being a valued member of a team of premier engineers.
In that case, we are determined to help build upon your existing foundation, while rapidly growing your individual and collaborative skills in this exciting and outstanding opportunity.
**Role and Responsibilities**- Responsible for Design and development of IP layouts used in DRAM chips.- Perform layout verification like LVS/DRC/EM, quality check and documentation.- Responsible for on-time delivery of block-level layouts with acceptable quality.- Demonstrate leadership Skill in planning, area/time estimation, scheduling, delegation and execution to meet project schedule/milestones in multiple project environment.- Guide and lead junior team-members in their execution of Sub block-level layouts & review their work.- Contribute to effective project-management.- Plan and document your layout, presenting material for global teams to review- Optimally connect with engineering teams in India, Japan the US, and other global teams to ensure the success of the layout project.
**Qualification/Requirements**- Must have 4+ years of experience in layout designs in advanced CMOS process.- Should be able to perform IP layout development and physical verification activities for complex designs as per provided specifications.- Should have expertise in layout area and routing optimization, design rules, yield and reliability issues.- Good understanding of layout fundamentals i.E.
Electro-migration, Latch-up, coupling, crosstalk, IR-drop, parasitic analysis, matching, shielding, etc.- Should have adequate knowledge of schematics, interface with circuit designer and CAD team.- Understanding layout effects on the circuit such as speed, capacitance, power and area etc