.Our vision is to transform how the world uses information to enrich life for all.Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever.Our Opportunity Summary:For more than 43 years, Micron Technology, Inc. has redefined innovation with the world's most advanced memory and semiconductor technologies.
We're an international team of visionaries and scientists, developing groundbreaking technologies that are transforming how the world uses information to enrich life.As a DRAM Engineering Group (DEG) Layout Designer at Micron Technology, Inc., you will be responsible for translating schematics into layout used for the creation of fabrication reticules.
You will be required to meet all engineering and process related criteria needed for an assigned DRAM product.
You will organize and prioritize logistics and resource allocations to meet scheduled deadlines, and proactively develop methodologies for issue resolution.
In this role, you will work with Design and other engineering groups to apply multiple layout techniques for the design and verification of digital and analog circuits.
You will be expected to understand various circuit design protocols, different fab processes, mask generation techniques, and tapeout processes and procedures.Our team vision is a continuing desire to develop your skills working in an inclusive diverse environment of multicultural teams across worldwide geographies!
Enabling the creative career path you deserve with a collaborative environment and groundbreaking technology and growing upon your imagination and creativity.Role and ResponsibilitiesResponsible for design and development of IP layouts used in DRAM chips.Perform layout verification like LVS/DRC/EM, quality check and documentation.Responsible for on-time delivery of block-level layouts with acceptable quality.Demonstrate leadership skills in planning, area/time estimation, scheduling, delegation and execution to meet project schedule/milestones in multiple project environments.Guide and lead junior team members in their execution of sub block-level layouts & review their work.Contribute to effective project management.Plan and document your layout, presenting material for global teams to review.Optimally connect with engineering teams in India, Japan, the US, and other global teams to ensure the success of the layout project.Qualification/RequirementsMust have 4+ years of experience in layout designs in advanced CMOS process.Should be able to perform IP layout development and physical verification activities for complex designs as per provided specifications.Should have expertise in layout area and routing optimization, design rules, yield and reliability issues.Good understanding of layout fundamentals, i.E