Layout Engineer

We are looking for Analog Layout Engineers!Requirements:STA timing constraints experience.Understand CMOS logic circuits.Perform IP layout development and physical verification activities for complex designs as per provided specifications.Good understanding of layout fundamentals i.E. Electro-migration, Latch-up, coupling, crosstalk, IR-drop, parasitic analysis, matching, shielding, etc.Adequate knowledge of schematics, interface with circuit designer and CAD team.Understanding layout effects on the circuit such as speed, capacitance, power and area.Excellent problem-solving skills in area, power, performance, and physical verification of custom layout.It is not necessary to meet all the requirements. If you have basic knowledge in some points of the stack and want to enter the semiconductor industry or continue your career in the same and are excited to keep learning, do not hesitate to apply!We have a place for everyone!Layout EngineerSueldo: $30,000 MXN - $40,000 MXN Mensual Categoría: Ingeniería Subcategoría: Ingeniero Localidad: México-Jalisco-Guadalajara Sector: Servicios Giro: Servicios de Outsourcing, Head Hunter y Consultoría en R.H. (Servicios) Tipo de contratación: Tiempo completo - Permanente Número de oferta: 19548059#J-18808-Ljbffr