Transforming the World with InformationMicron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence.Our Opportunity Summary:For more than 43 years, Micron Technology has redefined innovation with the world's most advanced memory and semiconductor technologies.We're an international team of visionaries and scientists developing groundbreaking technologies that transform how the world uses information to enrich life.As a DRAM Engineering Group (DEG) Layout Designer at Micron Technology, you will be responsible for translating schematics into layout used for the creation of fabrication reticules.Meet all engineering and process-related criteria needed for an assigned Dram product.
Organize and prioritize logistics and resource allocations to meet scheduled deadlines.Develop methodologies for issue resolution and work with Design and other engineering groups to apply multiple layout techniques for digital and analog circuits.Understand various circuit design protocols, fab processes, mask generation techniques, and tapeout processes and procedures.Join our inclusive diverse environment of multicultural Teams across worldwide geographies enabling the creative career path you deserve with a collaborative environment and groundbreaking technology.Role and Responsibilities:Design and development of IP layouts used in DRAM chips.Perform layout verification like LVS/DRC/EM, quality check and documentation.Responsible for on-time delivery of block-level layouts with acceptable quality.Leadership skills in planning, area/time estimation, scheduling, delegation and execution to meet project schedule/milestones.Guide junior team-members in their execution of Sub block-level layouts & review their work.Contribute to effective project-management.Plan and document your layout, presenting material for global teams to review.Optimally connect with engineering teams in India, Japan the US, and other global teams to ensure the success of the layout project.Qualification/Requirements:4+ years of experience in layout designs in advanced CMOS process.IP layout development and physical verification activities for complex designs as per provided specifications.Layout area and routing optimization, design rules, yield and reliability issues.Good understanding of layout fundamentals i.e.
Electro-migration, Latch-up, coupling, crosstalk, IR-drop, parasitic analysis, matching, shielding, etc.Adequate knowledge of schematics, interface with circuit designer and CAD team.Understanding layout effects on the circuit such as speed, capacitance, power and area etc.,Excellent problem-solving skills in solving area, power, performance and physical verification of custom layout.Experience with Cadence tools including Virtuoso schematic editor Virtuoso layout L, XL & Verification tools like Mentor Calibre - Proficient in Device Matching, Parasitic Analysis, Electron Migration, and Isolation Techniques.Leadership qualities and able to do multi-tasking as required.Self-motivated, hardworking, goal-oriented and excellent verbal and written communication skills.Knowledge of Skill coding and layout automation is a plus.Education:BE or MTech in Electronic/VLSI Engineering or related / Mechatronics.Estimated Salary: $120,000 - $180,000 per yearWe are an industry leader in innovative memory and storage solutions transforming how the world uses information to enrich life for all.With a relentless focus on our customers, technology leadership, and manufacturing and operational excellence, Micron delivers a rich portfolio of high-performance DRAM, NAND, and NOR memory and storage products through our Micron and Crucial brands.Every day, the innovations that our people create fuel the data economy, enabling advances in artificial intelligence and 5G applications that unleash opportunities — from the data center to the intelligent edge and across the client and mobile user experience.To learn more, please visit micron.com/careers