Unlock the Future of Memory and StorageMicron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence.We're an international team of visionaries and scientists, developing groundbreaking technologies that are transforming how the world uses information to enrich life.Our team vision is a continuing desire to develop your skills working in an inclusive diverse environment of multicultural Teams across worldwide geographies Enabling the creative career path you deserve with a collaborative environment and groundbreaking technology and growing upon your imagination and creativity.We are looking for an IP Layout Engineer in our DRAM and Emerging memory Group (DEG) at Micron Technology, Inc., As an IP Layout Engineer, you will be working with an exceptionally talented, passionate core team collaborating with peer teams crossing Micron global footprint, in a multiple projects-based environment.Role and Responsibilities:Design and development of IP layouts used in DRAM chipsPerform layout verification like LVS/DRC/EM, quality check and documentationResponsible for on-time delivery of block-level layouts with acceptable qualityDemonstrate leadership Skill in planning, area/time estimation, scheduling, delegation and execution to meet project schedule/milestones in multiple project environmentGuide and lead junior team-members in their execution of Sub block-level layouts & review their workContribute to effective project-managementPlan and document your layout, presenting material for global teams to review Optimally connect with engineering teams in India, Japan the US, and other global teams to ensure the success of the layout projectQualification/Requirements:Must have 5+ years of experience in layout designs in advanced CMOS processShould be able to perform IP layout development and physical verification activities for complex designs as per provided specificationsShould have expertise in layout area and routing optimization, design rules, yield and reliability issuesGood understanding of layout fundamentals i.e. Electro-migration, Latch-up, coupling, crosstalk, IR-drop, parasitic analysis, matching, shielding, etc.Should have adequate knowledge of schematics, interface with circuit designer and CAD teamUnderstanding layout effects on the circuit such as speed, capacitance, power and area etc.,Excellent in problem-solving skills in solving area, power, performance and physical verification of custom layoutExperience with Cadence tools including Virtuoso schematic editor Virtuoso layout L, XL & Verification tools like Mentor Calibre- Proficient in Device Matching, Parasitic Analysis, Electron Migration, and Isolation TechniquesShould have leadership qualities and able to do multi-tasking as requiredShould be able to work in a team environment and able to guide and provide technical support to the fellow team membersSelf-motivated, hardworking, goal-oriented and excellent verbal and written communication skillsKnowledge of Skill coding and layout automation would be plusEducation:BE/BTech or MTech in Electronic/VLSI Engineering or equivalent; we will also consider exceptionally talented Diploma holders in electronic or VLSI engineering.$143,000 - $173,000 per annum, depending on experience and qualifications