Our vision is to transform how the world uses information to enrich life for all. Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever.
For more than 43 years, Micron Technology, Inc. has redefined innovation with the world's most advanced memory and semiconductor technologies. We're an international team of visionaries and scientists, developing groundbreaking technologies that are transforming how the world uses information to enrich life.
As a Principal/Senior Design Verification Engineer, you will work with a highly innovative and motivated design and verification team using state of the art memory technologies to develop the most advanced DRAM and Emerging memory products. You will be challenged by the complexity and difficulty of verifying high density memory chips (up to 32Gb) with huge scale of circuit capability (over 4M transistors), ultra-high speed designs, complex functionality which includes next Generation DDR/LPDDR (ex: DDR6, DDR5, LPDDR6, LPDDR5, HBM) and advanced low power and power management technologies. You will be responsible to evaluate the functionality and performance of the Full-chip and block-level circuit designs using different verification tools, techniques, and strategies. In addition, you will also need to provide solutions to help deliver a functionally correct design. Lastly, you will need to collaborate closely with Micron's various design, verification, and product engineering teams all over the world to ensure design project success.
What's Encouraged Daily: Lead and drive various verification projects and process improvements; including the effort to port-over the probe and burn DFT patterns into the verification flow.Provide verification support to the DRAM and Emerging Memory Design Engineering teams by simulating, analyzing, and debugging pre-silicon full-chip and block-level designs.Develop SystemVerilog testbench infrastructure (e.g. UVM/Non-UVM and Constrained Random Verification Methodology).Responsible for test plan execution, running regressions, code and functional coverage closure.Assist product engineering teams with circuit and simulation support during post-silicon validation phase.Analyze gaps within the verification flow and methodology and provide solutions to address them.Develop, run, and maintain verification test benches and vectors using industry standard and in-house developed programs.Write test patterns/vectors and monitors to enhance the functional coverage for all DRAM and Emerging Memory architectures and features.Automate the collection of simulation data through writing software scripts to improve efficiency.Maintain and enhance in-house developed verification programs and tools.Collaborate closely with international colleagues to develop new verification methodologies and strategies to take on the future challenges in DRAM and Emerging Memory design.Mentor junior verification engineers.How To Qualify: BS in Electrical Engineering, Computer Engineering or equivalent with at least 7 years of industry experience.Deep understanding in CMOS and DRAM circuit design and operation.Familiarity with SystemVerilog testbench/UVM/Constrained Random verification methodology would be a strong plus.Fluent in writing simulation test patterns and vectors.Good debugging and problem-solving skills.Must possess good communication skills and ability to work well in a team environment.Self-driven, dedicated and the ability to multitask.Good programming fundamentals with knowledge in any scripting language.What Sets You Apart: Previous experience technically leading a team of engineers and mentoring junior engineers would be a strong plus.Good understanding of ASIC design flow including RTL design, verification, logic synthesis, and timing analysis.Familiarity with the DRAM DFT flow and DFT verification.Good understanding of ASIC design flow including RTL design, verification, logic synthesis, and timing analysis.Familiarity with digital and analog simulation methodology and tools, i.e., Finesim, Hspice, Hsim, and Verilog.Familiarity with RTL development for logic or mixed-signal circuits.
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