At Micron, we are committed to transforming how the world uses information to enrich life for all.We are seeking a highly skilled and motivated Senior Layout Designer to join our DRAM Engineering Group (DEG) Design Methodology team. As a key member of this team, you will play a vital role in creating innovative layouts that support our Commodity, Mobile, and Emerging R&D Design, Process, and Product Engineering customers.This is an exceptional opportunity to showcase your expertise in CMOS device physics and electrical characteristics through your outstanding designs. You will have the chance to work on mask generation and reticle design, collaborating closely with cross-functional teams to ensure seamless delivery.Key Responsibilities:Collaborate with customers to plan and document layouts, ensuring they meet Design and Process customer specifications.Verify layout quality using DRC, LVS, and other verification tools, both vendor-supplied and in-house.Apply Design Rules, interpreting and implementing them effectively, while collaborating with Process customers on CMOS process knowledge.Develop and document layout tools and methodologies to enhance quality, either through CAD or coding efforts.Identify issues and provide innovative solutions through effective communication.Lead sections of the layout design, coordinating with local and global teams to ensure quality for Design and Process customers.Requirements & Qualifications:A minimum of 5 years of experience in custom layout with advanced CMOS process.Expertise in layout area and routing optimization, design rules, yield, and reliability issues.A good understanding of layout fundamentals, including electro-migration, latch-up, coupling, crosstalk, IR-drop, parasitic analysis, matching, shielding, etc.Adequate knowledge of CMOS circuits/schematics and interface with circuit designers and CAD teams.Understanding of layout effects on the circuit, such as speed, capacitance, power, and area.Excellent problem-solving skills in solving area, power, performance, and physical verification of custom layouts.Experience with Cadence tools, including Virtuoso schematic editor, Virtuoso layout, L, XL, and Verification tools like Mentor Calibre. Proficient in Device Matching, Parasitic Analysis, Electron Migration, and Isolation Techniques.Leadership qualities and ability to multitask as required.Ability to work in a team environment and guide and provide technical support to fellow team members.Self-motivated, hardworking, goal-oriented, and excellent verbal and written communication skills.Knowledge of Skill coding and layout automation is a plus.Preferred Qualifications:Experience in Synopsys IC Compiler II or Cadence Innovus.Education:BS or MS in Electronic/VLSI Engineering or equivalent.