Our vision is to transform how the world uses information to enrich life for all. Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. Micron is THE place for you to expand your career by working on key projects and developing the leader in you We provide online learning opportunities and on-the-job training to upgrade your skills. We have a dedicated Micron University for your online learning. Our focus is empowering our customers' latest and the greatest innovations across a wide spectrum of industries and applications—so your work as a Micron team member can have a broad impact. And thanks to our welcoming yet fast-paced work environment, it is easy to collaborate with fellow team members to get difficult problems solved and turn customers' dreams into reality faster. The Senior Manager of Memory CAD Guadalajara is a technical leadership role within the Engineering Automation (EA) organization at Micron. The EA organization delivers DTK (Design Technology Kit) collateral, environments, tools and flows for the design, implementation, verification, and tape out of custom memory designs. These CAD tools and collateral enable DRAM, NAND, and other emerging memory designs on a range of industry-leading Micron-developed process nodes. Responsibilities: Lead the day-to-day support of CAD tools, flows and collateral provided by functionally organized CAD teams worldwide to DRAM design teams at the Guadalajara DEG Design Center. The tools and flows enable all aspects of mixed-signal, transistor-level custom IC design including logical design, custom layout, parameterized cells, automated place and route tools, physical design verification (LVS, DRC), ERC, Layout Parasitic Extraction, pre and post layout netlisting and simulation, digital and analog circuit simulation, timing and power analysis, reliability simulation and analysis (including HCI, BTI, EM/IR), tape out and mask generation.Drive close collaboration with DRAM design, layout, and verification methodology teams to propose and co-develop capabilities outstanding or under supported by EDA vendors and deploy best in class practices and methodologies consistently to DRAM designs worldwide.Drive research and development at the intersection of IC Design Automation and Machine Learning to envision, scope, develop and deliver solutions benefiting IC design.Establish and grow university relationships in the local and regional Guadalajara area to foster partnered research and development in design automation tools with an emphasis on data science and machine learning applications to EDA. Qualifications: Bachelor or preferably Masters/PhD in Computer Engineering, Computer Science or Electrical Engineering(15-20) + years of direct CAD or Design experience in mixed-signal, custom IC design flowsExperience leading highly technical IC Design or CAD teams distributed worldwideFamiliarity with memory design preferred (DDR3/4/5, LP3/4/5, HBM, NAND)Knowledge of CMOS circuit design, layout and verification, and in-depth experience supporting some of these areasCMOS transistor level design, logical design and netlistingCMOS digital and analog layout, Cadence Skill, and parameterized cellsAutomated place and route toolsLVS, DRC, LPE flowsERC flows, static and dynamic circuit checksCircuit simulation including nanometer scale MOS and interconnect effectsDigital simulation and verification flows (System Verilog/UVM test benches and coverage systems)Power delivery network simulation and analysisReliability flows such as HCI, BTI, EM/IR, crosstalkMask generation and tape out basicsExperience qualifying vendor tools and internally developed software releasesExperience developing software prototypes for innovative ideas in IC design, layout, and analysisExperience running agile (software) sprints is a plusExperience with Machine Learning algorithms and applicationsExperience and record of accomplishment delivering production-grade ML applications in IC Design (one or more areas including custom design, layout, logic and timing verification, circuit simulation and physical design verification)Comfortable directing and leading risky/uncertain innovative ML developmentExcellent communication and problem-solving skills are requiredStrive to continuously learn, develop new skills, and self-improve