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Senior Verification Engineer - Dram Design

Detalles de la oferta

.Our vision is to transform how the world uses information to enrich life for all.Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever.For more than 43 years, Micron Technology, Inc. has redefined innovation with the world's most advanced memory and semiconductor technologies. We're an international team of visionaries and scientists, developing groundbreaking technologies that are redefining how the world uses information to enrich life.Micron is searching for its next Principal/Senior Design Verification Engineer!In this role, you will work with a highly innovative and motivated design and verification team using innovative memory technologies to develop the most sophisticated emerging & DRAM memory products. Validate high density memory chips (up to 32Gb) with intricate circuitry, ultra-fast designs, and advanced functionality, including DDR/LPDDR technologies (e.G., DDR6, DDR5, LPDDR6, LPDDR5, HBM). Equivalent experience in DDR5 or relevant technologies will be considered. You will be responsible to evaluate the functionality and performance of the Full-chip and block-level circuit designs using different verification tools, techniques, and strategies. In addition, you will also need to help deliver a functionally accurate design. Lastly, you will need to collaborate closely with Micron's various design, verification, and our global engineering teams to ensure design project success.What's Encouraged Daily:Lead and drive various verification projects and process improvements; including the effort toport-over the probe and burn DFT patterns into the verification flow.Provide verification support to the DRAM & Emerging Memory Design Engineering teams by simulating, analyzing, and debugging pre-silicon full-chip & block-level designs.Develop SystemVerilog testbench infrastructure (e.G. UVM/Non-UVM and Constrained Random Verification Methodology)Responsible for test plan execution, running regressions, code and functional coverage closureAssist product engineering teams with circuit and simulation support during post-silicon validation phase.Analyze gaps within the verification flow and methodology and provide solutions to address them.Develop, run, and maintain verification test benches and vectors using industry standard and inhouse developed programs.Write test patterns/vectors and monitors to enhance the functional coverage for all DRAM & Emerging Memory architectures and features.Automate the collection of simulation data through writing software scripts to improve efficiency.Maintain and improve inhouse developed verification programs and tools.Collaborate closely with international colleagues to develop new verification methodologies and strategies to tackle the future challenges in DRAM and Emerging Memory design.Mentor junior verification engineers


Salario Nominal: A convenir

Fuente: Jobtome_Ppc

Requisitos

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