**Position Title: Sr. Digital Low Power Implementation Engineer (100% remote)****Location: 100% remote / work from home****Full-time: Salary + Benefits + Bonuses or Contractor**Responsible for creating turn-key solutions to support cutting-edge Cellular IoT device. This is a unique opportunity to define a groundbreaking new system with few legacy constraints.As a Sr. Digital Implementation Engineer, you will own the UPF delivery (to Design Verification and Physical Design) of various blocks and chip top level by ensuring the integrity and quality of the libraries and models and tool inter-operability. This position requires expert knowledge of Low Power ASIC implementation flow (including STA/DFT and IP integration)Define and document UPF-based low power methodology and scripts/flowsUPF hand-off checks (Conformal-LP, Xcelium, Genus/Innovus)UPF requirements and generation for defining power intent (at ip, block and chip level)Interface with Physical Design for design partitioning, floorplan and timing closureAnalyze UPF implementation results and facilitate design changes and ECOs with front-end and back-end teamsMinimum Qualifications:Expert knowledge and significant experience with UPF-based low power ASIC Implementation Flow, UPF Generation/Validation and Timing ClosureExperience in low power design issues, tools, and methodology including UPF power intent specificationFamiliarity with Synthesis (Cadence), DFT (Tessent) and back-end (Cadence) toolsProficient in Verilog/SV/Tcl/Perl/PythonHighly motivated to debug and resolve CAD tool flow issuesSelf-starter with good analytical, problem solving and communication skillsBachelor's degree in Electrical Engineering, a related discipline, or equivalent experienceDesired Qualifications:Experience with IP integrationExperience with Cadence UPF and ECO FlowExperience with Clock Domain Crossing (CDC) AnalysisExperience with timing corners and library modelsProven track record of successful deep submicron technology node tapeout (including Silicon bring-up)Detailed hands-on knowledge of all aspects of timing closure (including OCV, noise, crosstalk, IR-drop, power/voltage domains/UPF, DFT)
