Sr Eng-Deg Design Method-Layout

Detalles de la oferta

Our team transforms how the world uses information to enrich life. We innovate memory and storage solutions that accelerate information into intelligence. We are seeking a skilled Layout Designer to join our DRAM Engineering Group. As a Layout Designer, you will create innovative layouts for our customers. You will have the opportunity to showcase your expertise in CMOS device physics and electrical characteristics. You will also work on mask generation and reticle design. Responsibilities:Plan and document the layout in collaboration with Design customers.Verify layout quality using DRC, LVS, and other verification tools.Interpret and apply Design Rules, ensuring they are checking as intended.Develop and document layout tools and methodologies to enhance quality.Identify issues and provide innovative solutions.Lead sections of the layout design, coordinating with local and global teams.Qualifications & Skills:5+ years of experience in custom layout with advanced CMOS process.Expertise in layout area and routing optimization, design rules, yield and reliability issues.Good understanding of layout fundamentals, including Electro-migration, Latch-up, coupling, crosstalk, IR-drop, parasitic analysis, matching, shielding, etc.Adequate knowledge of CMOS circuits/schematics, interface with circuit designer and CAD team.Understanding layout effects on the circuit such as speed, capacitance, power and area etc.Excellent problem-solving skills in solving area, power, performance and physical verification of custom layout.Experience with Cadence tools including Virtuoso schematic editor Virtuoso layout L, XL & Verification tools like Mentor Calibre - Proficient in Device Matching, Parasitic Analysis, Electron Migration, and Isolation Techniques.Leadership qualities and multi-tasking abilities.Self-motivated, hardworking, goal-oriented and excellent verbal and written communication skills.Knowledge of Skill coding and layout automation is a plus.Preferred Qualifications:Experience in Synopsys IC Compiler II or Cadence Innovus.Education:BS or MS in Electronic/VLSI Engineering or equivalent


Fuente: Whatjobs_Ppc

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