Sr Eng-Deg Design Method-Layout

Detalles de la oferta

Transforming Information into IntelligenceMicron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever.We are seeking a skilled and motivated Layout Designer to join our DEG (DRAM Engineering Group) Design Methodology group.
As a Layout Designer, you will play a vital role in creating innovative layouts to support our Commodity, Mobile, and Emerging R&D Design, Process, and Product Engineering customers.Responsibilities:Plan and Document Layouts: Collaborate with Design customers to ensure layouts meet Design and Process customer specifications.Verify Layout Quality: Use DRC, LVS, and other verification tools to ensure layout quality.Apply Design Rules: Interpret and apply design rules, ensuring they are checked as intended, and collaborate with Process customers on CMOS process knowledge.Develop Tools and Methodologies: Create and document layout tools and methodologies to enhance quality through CAD or coding efforts.Solve Issues: Identify issues and provide innovative solutions through effective communication.Lead Sections: Coordinate with local and global teams to ensure quality for Design and Process customers.Qualifications & Skills:5+ years of experience in custom layout with advanced CMOS process.Expertise in layout area and routing optimization, design rules, yield, and reliability issues.Good understanding of layout fundamentals, including Electro-migration, Latch-up, coupling, crosstalk, IR-drop, parasitic analysis, matching, shielding, etc.Adequate knowledge of CMOS circuits/schematics and interface with circuit designer and CAD team.Understanding of layout effects on circuits such as speed, capacitance, power, and area.Excellent problem-solving skills in solving area, power, performance, and physical verification of custom layout.Experience with Cadence tools, including Virtuoso schematic editor and Virtuoso layout, and verification tools like Mentor Calibre.Leadership qualities and ability to multitask as required.Ability to work in a team environment and guide fellow team members.Self-motivated, hardworking, goal-oriented, and excellent verbal and written communication skills.Knowledge of Skill coding and layout automation is a plus.Preferred Qualifications:Experience in Synopsys IC Compiler II or Cadence Innovus.Education:BS or MS in Electronic/VLSI Engineering or equivalent.


Salario Nominal: A convenir

Fuente: Whatjobs_Ppc

Requisitos

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