Our vision is to transform how the world uses information to enrich life for all. Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever.
Job DescriptionMicron is THE place for someone to expand their career by working on key projects and developing themself into the leaders of tomorrow! We provide online learning opportunities and on-the-job training to upgrade your skills. We have a dedicated Micron University for your online learning!
We focus on empowering our customers' latest and the greatest innovations across a wide spectrum of industries and applications—so your work as a Micron team member can have a broad impact. And thanks to our welcoming yet fast-paced work environment, it is easy to collaborate with fellow team members to get difficult problems solved and turn customers' dreams into reality faster.
The Senior/Principal HBM CAD Engineer is a technical leadership role within the Engineering Automation (EA) organization at Micron. We deliver DTK (Design Technology Kit) collateral, environments, tools and flows for the design, implementation, verification, & tape out of custom memory designs. These CAD tools and collateral enable DRAM, NAND, and other emerging memory designs on a range of industry-leading Micron-developed process nodes.
Specific focus:TSMC mixed-signal, custom-digital experience like ADE-XL, Spectre, synthesis tools (DC/Genus), implementation tools (ICC2, Innovus), STA (Primetime, Tempus), EMIR (Redhawk, Voltus etc), functional & timing verification of cell-based designs (dynamic simulation and static analysis). Our ideal candidates combine pure digital RTL2GDS blocks with custom digital & analog blocks using TSMC collateral/environments for high speed, low power, area-efficient designs.
Responsibilities:Own the day-to-day support of CAD tools, flows and collateral provided by functionally organized CAD teams worldwide to HBM design teams at the Dallas or Folsom Design Center. The tools and flows enable all aspects of mixed-signal, transistor-level custom IC design including logical design, custom layout, parameterized cells, automated place and route tools, physical design verification (LVS, DRC), ERC, Layout Parasitic Extraction, pre and post layout net listing and simulation, digital and analog circuit simulation, timing and power analysis, reliability simulation and analysis (including HCI, BTI, EM/IR), tape out and mask generation.Drive close collaboration with HBM design, layout, & verification methodology teams to propose and co-develop capabilities outstanding or under supported by EDA vendors and deploy outstanding practices and methodologies consistently to High Bandwidth Memory designs worldwide.Drive research and development at the intersection of IC Design Automation and Machine Learning to envision, scope, develop and deliver solutions benefiting IC design.Qualifications:Bachelor or preferably Masters/PhD in Computer Engineering, Computer Science or Electrical Engineering(5-15) + years of direct CAD or Design experience in Digital RTL to GDS Flows.Familiarity with memory design preferred (DDR3/4/5, LP3/4/5, HBM, NAND)Knowledge of CMOS circuit design, layout and verificationKnowledge and experience vetting and deploying sophisticated EDA software flowsExperience qualifying vendor tools and internally developed software releasesExperience developing software prototypes for innovative ideas in IC design, layout, and analysisExperience running agile (software) sprints is a plusExperience with Machine Learning algorithms and applicationsExcellent communication and problem-solving skills are requiredStrive to continuously learn, develop new skills, and self-improve
#J-18808-Ljbffr